In the application specific integrated circuit (ASIC) industry, it is desirable to integrate an entire system or subsystem on one integrated circuit chip. The ability to so integrate increases the economy and reliability of the system or subsystem. However, to take advantages of this integration, all the system components are preferably implemented in the same process technology. Such integration becomes a significant problem, for example, in the case of mixed analog and digital system. One way to integrate mixed analog and digital system on one chip is to employ a special process technology for the analog systems in addition to the process technology for the digital portion of the chip. For most ASIC chips, only a small portion of the chip is used for analog circuits while by far the greater portion of the chip is used for digital circuits. Hence, devoting a special process technology for adding analog process modules in the digital process, such as capacitor implants and double poly, is expensive. One solution to the problem is to design certain analog components in the digital process. In this approach, careful circuit design is necessary to overcome the large offset voltages, and unpredictable amplification and lack of a good capacitor in a typical digital technology.
The comparator is a frequently used analog circuit on ASIC chips; for example, it is used in analog to digital converters. Therefore, it is desirable to provide a comparator circuit design that is feasible for implementation in a typical digital technology.
Referring to FIG. 1A, a circuit diagram of a conventional comparator is demonstrated. The comparator in accordance to prior art consists of three inverters, two capacitors and several switches. Moreover, a reference voltage Vref and an inputting voltage Vin are coupled with the comparator and the voltage difference between the voltage sources is amplified. Additionally, the comparator acts as an analog to digital converter. In the following description, the circuit design of the conventional comparator will be explained.
Referring to FIG. 1A, a reference voltage Vref and an inputting voltage Vin are respectively coupled with one terminal of a capacitor 110 through a switch CKvin and a switch CKvref. Moreover, the another terminal of the capacitor 110 is coupled with the inputting terminal of an inverter 120 and the outputting terminal of the inverter 120 is coupled with one terminal of a capacitor 130. Meanwhile, the outputting terminal of the inverter 120 is coupled with the inputting terminal of it through a switch az1. Then, the another terminal of the capacitor 130 is coupled with the inputting terminal of an inverter 140 and the outputting terminal of the inverter 140 is coupled with the inputting terminal of an inverter 150. Meanwhile, the outputting terminal of the inverter 140 is coupled with the inputting terminal of it through a switch az2. Finally, an outputting voltage Vout is output from the outputting terminal of the inverter 150.
Thus, two voltage sources are input into the comparator according to FIG. 1A. After that, the voltage difference between both of the voltage sources is amplified and the amplified voltage difference is output from the outputting terminal of the comparator. Consequently, two analog signals are input into the inputting terminal of the comparator and one digital signals is output from the outputting terminal of the comparator. That is, the comparator is used as an analog to digital converter.
Referring to FIG. 1B, it is demonstrated that a timing diagram of clock signals for operating the switches in the conventional comparator according to FIG. 1A. It is supposed that the switches in FIG. 1A are NMOS transistors. As a high-level voltage is applied on the gate of an NMOS transistor, it will be turned on. Similarly, as a low-level voltage is input into the gate of an NMOS transistor, it will be turned off.
Referring to FIG. 1B, the switch az1, the switch az2 and the switch CKvin are turned on and the switch CKvref is simultaneously turned off. After that, the reference voltage Vref is input into the capacitor 110. Therefore, a voltage level is maintained in the capacitor 110 and it is equal to the voltage level of the inputting voltage Vin minus the threshold voltage Vth of the inverter 120. At the same time, the inverter 120 receives an negative feedback from the outputting terminal to the inputting terminal through the switch az1 and the inverter 140 receives an negative feedback through the switch az2, too.
Referring to FIG. 1B, after the capacitor is charged by the voltage source Vin, the switch az1 is firstly turned off. The switch az2 and the switch CKvin are then turned off and the switch CKvref is simultaneously turned on. Meanwhile, the reference voltage Vref is input into the capacitor 110 and the voltage at the input of the inverter 120 is equal to the voltage Vth+Vref-Vin. Subsequently, the voltage difference is amplified by the inverters 120, 140 and 150. Additionally, the capacitor 130 is used to save the offset of the inverter 120 and the inverter 140.
Referring to FIG. 1B, there have two phases for operating the switches in the timing diagram of clock signals. The phase A is a sampling period for charging the capacitor 110 by the inputting voltage Vin and the phase B is a comparing period for determining the voltage difference between the inputting voltage Vin and the reference voltage Vref.
A voltage comparison performed in a conventional comparator takes long time and the gain of the conventional comparator need very large. For a high gain of a comparator, the channel length of the inverter must be lengthened, but it slows the speed of the comparator down. It will be a trend that the size of integrated circuits scales down. However, as the size of a comparator is scaled down, the channel length of it should not be shortened in order to get a high gain. Therefore, a high-speed comparator without a long channel length is needed for high-density integrated circuits.